DIGITAL SYSTEMS ELECTRONICS

iten
Code
72345
ACADEMIC YEAR
2017/2018
CREDITS
12 credits during the 1st year of 9273 Electronic Engineering and Information Technology (L-8) GENOVA
SCIENTIFIC DISCIPLINARY SECTOR
ING-INF/01
LANGUAGE
Italian
TEACHING LOCATION
GENOVA (Electronic Engineering and Information Technology )
semester
Annual
Teaching materials

OVERVIEW

The course provides the foundations for digital system analisys and design. In the first part, we start from Boolean algebra and binary arithmetic, arriving to sequential networks design, using the Finite State Machines model and ASM diagrams. In the second part, the course introduces the microcomputers, with particular reference to "embedded" systems, machine language programming, interfacing with interrupt techniques and the microcomputer as system controller.

AIMS AND CONTENT

LEARNING OUTCOMES

Digital Design foundations: Boolean algebra, binary arithmetic, combinatorial and sequential networks. Finite State Machines. Programmable logic devices (FPGA), introduction to the languages for hardware description. Programmable systems (microcomputers): architecture, machine language programming, interfacing, controllers, embedded systems.

AIMS AND LEARNING OUTCOMES

The course defines the basics for the analisys and the design of digital systems. In the first part, after introducing Boolean algebra and binary arithmetic, the course covers the methods of analysis and design of combinational and sequential digital networks, using the technique of Finite State Machines model, with the help of the ASM diagrams. In the second part, after having defined the elements of the architecture of a microcomputer, the course introduces the development of "embedded" systems, particularly with regard to machine language programming, interfacing with external devices, to the interrupt techniques and the use microcomputer as system controller.

TEACHING METHODS

The course consists of about 120 hours in the classroom, in which lectures and exercises are alternated as necessary. They are also provided for 25 laboratory sessions dedicated to the analysis, design, simulation and implementation of digital circuits. The laboratory exercises can be carried out remotely, with the site's support AulaWeb Course.

SYLLABUS/CONTENT

Introduction to the course, information representation, Boolean functions and logic networks, Shannon expansion theorem, standard combinational circuits.

Minimization of Boolean functions, Karnaugh maps, hints of algorithmic methods.

Binary arithmetic, binary codes and operations, complements, conversions, major arithmetic-logical architectures, error detection codes, alphanumeric codes.

Introduction to sequential circuits, timing concepts, Flip-Flops (SR FF, FF D Latch, FF JK, D and E PET), registers, counters, sequential networks analysis.

Introduction to Finite State Machine (FSM) and ASM charts (status block, conditional block, conditioned outputs). Project examples and exercises, state assignment criteria, hint of asynchronous FSM.

Electronic devices and components, packaging, programmable devices (FPGA), overview of available devices, project examples.

Basic elements of a digital computer: Processing Unit, Memory, Input / Output Units (Von Neumann architecture). Bus based systems: addressing, data transfer and control signals. Solid-state memory devices: static read / write memories, read-only memories.

Architecture of microprocessors: registers, calculating unit, sequencer. Programs and instructions: fetch, decode, execute phases. Machine language. Mnemonic format of instructions and assembly language. Example of execution of a generic instruction. Timings. Distinction between CISC and RISC processors.

Introduction to assembly programming. Language syntax. Comparison to the high-level languages. Addressing modes. Instruction set and their functional classification. Data transfer instructions. Arithmetic and logical instructions. Jump instructions. The stack structure, call and return instructions, subroutines. Control instructions and "hidden" instructions.

Hardware design of a microprocessor system. Clock generator, reset circuits, address decoder. Memory banks design. 

Input/Output evices. Basic techniques of parallel and serial interfacing. Handshake between devices. Introduction to programmable input / output devices. Interrupt techniques. Management of device recognition and priority. The interrupt controller.

The microcomputer as a controller of a digital system. Introduction to "embedded" systems. Introduction to RISC microprocessors.

RECOMMENDED READING/BIBLIOGRAPHY

The course handouts, available (in pdf) on Aulaweb page of the course

TEACHERS AND EXAM BOARD

Office hours: The teacher is available to answer questions on topics of the course, by appointment (to be defined by e-mail).

Exam Board

GIULIANO DONZELLINI (President)

DAVIDE ANGUITA

PAOLO GASTALDO

DOMENICO PONTA

RODOLFO ZUNINO

LESSONS

TEACHING METHODS

The course consists of about 120 hours in the classroom, in which lectures and exercises are alternated as necessary. They are also provided for 25 laboratory sessions dedicated to the analysis, design, simulation and implementation of digital circuits. The laboratory exercises can be carried out remotely, with the site's support AulaWeb Course.

Class schedule

All class schedules are posted on the EasyAcademy portal.

EXAMS

EXAM DESCRIPTION

The examination of the course consists of two written exams (partial tests) and an oral examination. In the same appeal you can execute one or both partial written tests. The first partial test involves the design of a digital system controlled by MSF (topics of the first part of the course). The second partial test focuses on the design of a system based on a microcomputer (topics of the second part of the course). Both tests must be carried out without the use of computers.

ASSESSMENT METHODS

The time available to perform a partial written test is 1h 30'. To each of the partial tests can be added one "bonus" point, if carried out and delivered only once. It is permitted to retire from the partial written exam, keeping the bonus. The final grade will be 'calculated as follows:

Max 13 points for the first partial test
Max 13 points for the second partial test
± 5 points for the oral examination
+ 2 Total bonus point.

The oral exam is mandatory. To take the oral test and the student must have executed both partial tests, reporting a total score (excluding bonus) of at least 13, with a minimum of 5 points for each test.

Exam schedule

Date Time Location Type Notes
15/01/2018 09:30 GENOVA I Scritto Parziale
15/01/2018 11:00 GENOVA II Scritto Parziale Aula: da definirsi * La prima prova parziale inizia alle 9:30 e termina alle 11:00. La seconda prova parziale inizia alle 11:15 e termina alle 12:45. * Tutte le prove di ESD valgono anche per ESD 1 e ESD 2 del CL3 EO ordinamento 509. Le prove orali sono da concordare direttamente con il docente
12/02/2018 09:30 GENOVA I Scritto Parziale
12/02/2018 11:00 GENOVA II Scritto Parziale Aula: da definirsi * La prima prova parziale inizia alle 9:30 e termina alle 11:00. La seconda prova parziale inizia alle 11:15 e termina alle 12:45. * Tutte le prove di ESD valgono anche per ESD 1 e ESD 2 del CL3 EO ordinamento 509. Le prove orali sono da concordare direttamente con il docente
11/06/2018 09:30 GENOVA I Scritto Parziale
11/06/2018 11:00 GENOVA II Scritto Parziale Aula: da definirsi * La prima prova parziale inizia alle 9:30 e termina alle 11:00. La seconda prova parziale inizia alle 11:15 e termina alle 12:45. * Tutte le prove di ESD valgono anche per ESD 1 e ESD 2 del CL3 EO ordinamento 509. Le prove orali sono da concordare direttamente con il docente
09/07/2018 09:30 GENOVA I Scritto Parziale
09/07/2018 11:00 GENOVA II Scritto Parziale Aula: da definirsi * La prima prova parziale inizia alle 9:30 e termina alle 11:00. La seconda prova parziale inizia alle 11:15 e termina alle 12:45. * Tutte le prove di ESD valgono anche per ESD 1 e ESD 2 del CL3 EO ordinamento 509. Le prove orali sono da concordare direttamente con il docente
10/09/2018 09:30 GENOVA I Scritto Parziale
10/09/2018 11:00 GENOVA II Scritto Parziale Aula: da definirsi * La prima prova parziale inizia alle 9:30 e termina alle 11:00. La seconda prova parziale inizia alle 11:15 e termina alle 12:45. * Tutte le prove di ESD valgono anche per ESD 1 e ESD 2 del CL3 EO ordinamento 509. Le prove orali sono da concordare direttamente con il docente